1. Field of the invention
This invention refers to a data processing unit having facilities for changing the priority level of data processing circuits.
Particularly the data processing unit comprises a plurality of hardware data processing priority circuits, a memory for storing a plurality of microinstructions and, for each of said priority levels, a program counter register for addressing said microinstructions in succession and an addressing register for storing the addresses of the operands of said microinstructions.
2. Description of the Prior Art
As is known, most electronic computers are provided with a plurality of processing priority levels and each of such levels executes a predetermined number of processing operations. For instance, in a three level computer, the level three (having the less priority) is used for computing and controlling the data, while the levels one and two are used for the character interchange with the peripheral units.
Several systems are known for shifting from a priority level to another one having a less priority as a consequence of particular events occurring during the data processing. For instance, one of such events occurs when a computer is processing data by using hardware of the priority level having order 3 and it is interrupted by a peripheral unit requesting a "character interchange operation". At this moment the computer stops the processing in progress at the level 3 and manages the character interchange operation by using hardware of the level 2. As is known, such management is executed by the interrupt facility which allows the "overlapping" operation of both the character interchange at level 2 and the processing at level 3.
When the character interchange has been performed, the peripheral unit communicates this event in a known manner to the computer which checks up on the received characters, for instance the computer may carry out a parity check operation by means of a redundancy polynominal in the case where the characters have been transmitted from a magnetic substrate reading unit. This checking operation is generally carried out by a specific program and executed at level 3 which is, as said above, the level wherein all checking operations take place. When the character interchange operation has finished, the data processing unit must switch from the level 2 (which is the level whereat the interchange occurred) to the service microprogram of the level three to manage the checking operation of the characters and at the same time it is required to reserve the microprogram of the level, the execution of which is already in progress.
In a known system these operations are carried out separately by means of two instructions: one instruction executes the "reservation" operation, namely it transfers the program counter contents of the level three onto a suitable memory register; the other instruction carries out the shifting operation from the level 2 onto a special memory cell whereon is stored the address of the first service program instruction to be executed at the level three.
Such a system has two disadvantages: the first being that the control switching occurs by means of the execution of two instructions, wherefore the time required for switching the control from the level 2 onto the level 3 is the sum of the execution times of the two instructions. The second disadvantage being that afterwards it is still required to transfer the contents of the memory cell addressed by the second instruction onto the program counter of the level three. Consequently the total time required for the control switching from the level two onto the level three must be further increased.